CiteSeerX - Document Details (Isaac Councill, Lee Giles, Pradeep Teregowda): CPU core complex (e200z0h) - Compatible with classic PowerPC instruction set - Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional RISC-V decided that variable-length compressed instruction set was a brilliant idea so they added it as an ISA base extention (That letter "C" you usually see in processor names (e.g. RV64GCV With VLE there isn't an e_and2i instruction that doesn't update CR. If your code doesn't rely on CR being preserved (likely the case) you could simply change e_and2i to e_and2i.. Your code would then look like: mfmsr r6 e_and2i. r6,0x7fff mtmsr r6 Alternatively you can use the 3 operand form e_andi that doesn't update CR. It would look like: powerpc architecture and assembly language an instruction set architecture (isa) specifies the programmer-visible aspects of a processor, independent of implementation • number, size of registers • precise semantics, encoding of instructions the powerpc isa was jointly defined by ibm, apple, and motorola in 1991 ibm has released the power … VLE optimizes code density by encoding 32-bit PowerPC instructions into mixed 16 and 32-bit instructions, reducing code footprint by up to 30 percent. 16 and 32-bit instructions may be freely intermixed. VLE is supported by most Power Architecture toolchains and is available on all four of the e200 family cores. Signal Processing Engine (SPE) A user-defined instruction has a configurable format and is a true extension of the PowerPC instruction set architecture (ISA). Enabling the APU Controller The PowerPC MSR register must be configured before the processor can use the APU controller. Table 4-1 describes the APU controller-related bits in the MSR. Instruction Classes SYStem.Option.NOTRAP Use alternative software breakpoint instruction 16 SYStem.Option OVERLAY Enable overlay support 17 SYStem.Option TranslationSPACE Identify user and hypervisor modes 17 SYStem.Option ZoneSPACES Enable symbol management for zones 18 I am writing an ELF32 parser and disassembler for PowerPC. Does anyone knows how to detect if the file is using VLE architecture from ELF header? I see that IDA can do it automatically. The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. Generate code for Freescale PowerPC VLE instructions. -mvsx. Generate code for processors with Vector-Scalar (VSX) instructions. Book I, Power ISA User Instruction Set Architecture, covers the base instruction set and related facilities available to the application programmer. It includes five chapters derived from APU function, including the vec-tor extension also known as Altivec. Book II, Power ISA Virtual Environment Architecture, StackAnalyzer for PowerPC automatically determines the worst-case stack usage of the tasks in your appli­cation. The analysis results are shown as annotations in the call graph and control flow graph. General 32-bit and 64-bit PowerPC processors with PPC and VLE instruction set; AltiVec is not supported; Supported CPUs include, but are not StackAnalyzer for PowerPC automatically determines the worst-case stack usage of the tasks in your appli­catio